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Grouped Clock Gated Flip-Flop Array for Low Power Applications

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In real time processors, main part of power dissipation occurs due to dynamic power consumption. Clock gating is used to avoid unwanted switching activity but it causes area and power overheads due to extra logic gates. To avoid overheads, it needs a clock grouping technique to group a several FFs driving by a same clock signal but it will not give a complete solution. Clock gated multi bit flip flop will give efficient result in terms of area and power. In multi bit flip flop, clock generation logic for slave nodes will be same; hence it will reduce the number of logic gate required for flip flop. Clock grouping will be done based on the position of bits and each group has a single multi bit flip flop. A common data driven clock gating logic is added to each group to reduce the power consumption.
Keywords:Clock gating, Clock network, Multi-bit flip-flops, Power reduction


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