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Design and Analysis of Adiabatic Logic Based Frequency Divider

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Frequency dividers are crucial circuits that are employed in PLLs and high-speed serialize/deserializers. The flip-flop-based frequency dividers are comprised of two D latches in cascade, and in a negative feedback configuration. The digital operation of this type of dividers provides the advantage of suppressing the sensitivity to waveform distortions. Furthermore, the flip-flop-based dividers achieve a wide bandwidth than other types of frequency dividers at low-to-medium range of frequencies. This paper presents a high-speed DFAL flip-flop-based frequency divider incorporating a new high-speed latch topology, which provides satisfactory performance for frequencies up to 17 GHz. This circuit is designed and simulated in a standard 0.18μm CMOS process. This architecture is primarily a master-slave flip-flop with a negative feedback. Thus frequency division is achieved. The designed circuit and the verification can be done in TANNER EDA.
Key Terms: adiabatic, digital circuit, DFAL, frequency divider, low power, stacking technology.
With the advances in VLSI technology, there is a great demand of portable devices that perform high speed computing and support multimedia applications. However, the increased functionality and high speed operation result in high power dissipation which eventually creates a need for low power design solutions. Different solutions both at the architectural and structural levels have been suggested. One possible approach is to adopt adiabatic logic style over conventional CMOS logic style for circuit design. Adiabatic logic style is more energy efficient than the conventional CMOS logic style [10]. A number of families based on adiabatic logic style have been proposed in literature. The common adiabatic logic families that are frequently used are 2PADCL, ECRL, ADL, QSER and GFCAL. The mentioned logic families however suffer from the drawbacks of amplitude degradation, large time delays and circuit complexity. In this paper a DFAL based frequency divider using stacking technology is proposed.
The common adiabatic logic families suffer from amplitude degradation, large time delays and circuit complexity. These drawbacks can be eliminated by using DFAL style. The DFAL style removes the diode from the charging and discharging path to overcome the above disadvantages. basic structure of a DFAL inverter is shown in Fig. 1a.The transistors M1, M2 implement the inverter.
The transistor M3 is added in series with the transistor M2 for discharging and recycling of the output node charge. Its usage reduces the power dissipation significantly because it acts as a low value resistance, as compared to other adiabatic logic families which use diodes in the discharging path.


  1. Changhua Cao and Kenneth K. O, “A Power Efficient 26-GHz 32:1 Static Frequency Divider in 130-nm Bulk CMOS”, IEEE Microwave and Wireless components letters VOL. 15, NO. 11, NOVEMBER 2005.
  2. Dickinson A G and J.S. Denker, “Adiabatic dynamic logic,” Solid- States Circuits, IEEE Journal, Vol.30, Issue3, Mar., 1995, pp.311-315
  3. Hamid Mahmoodi-Meimand, Ali Afzali-Kusha and Mehrdad Nourani,” Efficiency of Adiabatic Logic for Low-Power, Low-Noise VLSI” Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium Volume:1
  4. Himanshu Puri, Kshitij Ghai, Kirti Gupta, “A Novel DFAL Based Frequency Divider”, International Conference on Signal Processing and Integrated Networks, 2014
  5. Moon Y and D.K. Jeong, “An efficient charge recovery logic circuit,” Solid-States Circuits., IEEE Journal, Vol.31, Issue4, Apr., 1996, pp.514-522.
  6. Nazrul Anuar, Yasuhiro Takahashi, and Toshikazu Sekine, “Two Phase Clocked Adiabatic Static CMOS Logic and its Logic Family”, Journal of Semiconductor Technology and Science, VOL.10, NO.1, MARCH, 2010
  7. Reddy N S S, M. Satyam, and K. L. Kishore, “Cascadable adiabatic logic circuits for low-power applications,” IET Circuits, Devices and Systems, vol. 2, no. 6, pp. 518–526, 2008.
  8. Shipra Upadhyay, R. A.Mishra, R. K. Nagaria, and S. P. Singh, “DFAL: Diode-Free Adiabatic Logic Circuits”, Hindawi Publishing Corporation ISRN Electronics, Volume 2013, Article ID 673601, 12 pages
  9. Takahashi Y, Y. Fukuta, T. Sekine, and M. Yokoyama, “2PADCL: Two phase drive adiabatic dynamic CMOS logic,” in Proc. IEEE APCCAS, Dec., 2006, pp. 1486-1489.
  10. Y. Ye, and K. Roy, “QSERL: Quasi-static energy recovery logic,” Solid-States Circuits., IEEE Journal, Vol.36, Issue 2, Feb., 2001, pp. 239-248