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Low Power Design of Johnson Counter Using DDFF Featuring Dual Mode Logic

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Reducing power consumption in very large scale integrated circuits (VLSI) design has become an interesting research area. A new dual dynamic node hybrid flip-flop (DDFF) and a novel embedded logic module (DDFF-ELM) based on DDFF are introduced here. Both of them eliminate the drawbacks of existing high performance flip-flop designs. The proposed design mainly reduces the power consumption by eliminating the large capacitance present in the pre-charge node of several existing flip-flop designs by separately driving the output pull-up and pull-down transistors by following split dynamic node structure. This reduces the power up to 40% compared to conventional architectures of flip-flops. The DDFF and DDFF-ELM are compared with other state of the art designs by implementing a Johnson up-down counter. The DML is introduced in Johnson counter improve the speed performance by allowing the system to switch between static and dynamic modes of operation according to its requirements.
Key Terms: VLSI, flip flops, power dissipation, split dynamic nodes, DDFF-ELM, DML
Over the past decade, power consumption of VLSI chips has been continuously increasing. The need for low-power design is becoming a vital parameter in high-performance digital systems. There are numerous techniques being encountered for the design of low power VLSI circuits. Low power has made an important note that power dissipation has a consideration on performance and area. Static power and Dynamic power being the main components determining the power consumption in CMOS circuits[6]. In synchronous systems, high speed has been obtained using advanced pipelining techniques. In modern pipelined architectures, high speed demands a lower pipeline overhead. The overhead is the latency related with the pipeline elements, such as the flip-flops and latches. The design methodology and area and timing requirements determine the choice of latches and flip-flops[8]. Latches and flip-flips can be static or dynamic. A dynamic latch or flip-flop loses its content as time increases, while a static one retains its content regardless of elapse time. In the past few decades, lot of work has been done to improve the performance of the flip-flops. The flip-flops considered for analysis are PowerPC 603, Hybrid-Latch flip-flop (HLFF), Semi-dynamic flip-flop (SDFF), Conditional pre charge flip-flop (CPFF),conditional data mapping flip-flop (CDMFF) and Cross charge control flip-flop (XCFF). The main trade-offs of any flip-flop are very important for a design engineer when designing a circuit or for a tool that automates the process of design.
The DDFF offers a power reduction of up to 37% and 30% compared to the conventional flip-flops at 25% and 50% data activities, respectively. The aim of the DDFF-ELM is to reduce pipeline overhead. It presents an area, power, and speed efficient method to incorporate complex logic functions into the flip-flop. The performance comparisons made in a 90 nm UMC process show a power reduction of 27% compared to the Semi dynamic flip-flop, with no degradation in speed performance. The leakage power and process-voltage-temperature variations of various designs are studied in detail and are compared with the proposed designs. Also, DDFF and DDFF-ELM are compared with other state-of-the-art designs by implementing a 4-b synchronous counter and a 4-b Johnson up-down counter. The performance improvements indicate that the proposed designs are well suited for modern high-performance designs where power dissipation and latching overhead are of major concern.


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