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Design and Analysis of an Area Efficient and Low Power NEW-R2MDC FFT for MIMO OFDM in wireless Communication

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In this paper, an area-efficient low power fast fourier transform (FFT) processor is proposed for multi input multi output -orthogonal frequency division multiplexing (MIMO-OFDM) in wireless communication system. It consists of a modified architecture of radix-2 algorithm which is described as new radix-2 multipath delay commutation (New- R2MDC). Orthogonal frequency-division multiplexing is a popular method for high data rate wireless transmission. This paper describes the very large scale integration (VLSI) design of an area efficient new-r2mdc FFT for MIMO OFDM system targeted to future wireless communication systems. The very high speed integrated hardware description language (VHDL) simulation results have been tested practically by implementing in the Altera DE-2 field programmed gate array (FPGA) development board. Also the existing OFDM system has been tested with these FFT algorithms and their performances were analyzed with respect to occupation of area in FPGA and power consumption. A low-power and area efficient architecture enables the real-time operations of MIMO OFDM system.
Keywords:New-radix-2 multipath delay commutation, frequency division multiplexing, multi input multi output – orthogonal frequency division multiplexing, inverse fast fourier transform, fast fourier transform, discrete fourier transform
MIMO-OFDM is the efficient solution for transmitting and receiving the data over the long distance. The sub-carrier frequency has been chosen in our proposed MIMO OFDM transceivers so that cross-talk between the sub-channels are eliminated, hence the inter carrier guard bands are not required [1]. This greatly simplifies the design of both the transmitter and the receiver; unlike conventional frequency division multiplexing (FDM), a separate filter for each subchannel is not required [2]. The orthogonally allows for efficient modulator and demodulator implementation using the FFT algorithm [3]. OFDM transceiver is popular for wideband communications today by way of low-cost MIMO OFDM in wireless telecommunication system. It requires very accurate frequency synchronization between the receiver and they have reduced the complexity [4]. In transmitter; with frequency deviation, the sub-carriers shall no longer be orthogonal, causing inter-symbol interference (ISI) [5]. The 5/6 coding rate would be not effective for error correcting by a viterbi decoder [6]. This paper describes the VLSI implementation of the proposed new-R2MDC for MIMO OFDM systems, i.e., modified radix-2 multipath delay commutation pipeline FFT based MIMO OFDM system..
The radix-2 algorithm with multi delay commutation architecture is to support 4-channel 8, 16, 32, 64, 128, 512, 1024 and 2048-point FFT operations [7, 8]. We compare this proposed architecture with existing 8-point radix 2, radix 4 FFT and existing R2MDC FFT and also give the design and implementation results of the proposed FFT processor.


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