Performance of FIR Filter with Wallace Multiplier over FIR filter with Truncated Multiplier

Abstract
Performance analysis of finite impulse response (FIR) designs are presented by the concept of modified Wallace multipliers .This paper aims at reducing the leakage current , delays and power consumption of Wallace multiplier .This is accomplished by MCSA. An efficient verilog HDL has been written, successfully simulated and synthesized in Xilinx and the results shows that proposed design achieves the best delay and power than existing system which uses the concept of truncated multiplier.
Keywords:Faithful Rounding, Finite Impulse Response (FIR) filters, Truncated Multipliers, VLSI.
I.Introduction
Finite impulse response (FIR) digital filters are one of the most widely used fundamental devices performed in DSP systems, ranging from wireless communications to video and image processing. This paper proposes new parallel FIR filter structures, which are beneficial to symmetric coefficients in terms of the hardware cost, under the condition that the number of taps is a multiple of 2 or 3. The 5 parallel FIR structures gives low area and high speed compare to existing 4 parallel architecture , exploit the inherent nature of symmetric coefficients reducing half the number of multipliers in sub filter section at the expense of additional adders in preprocessing and post processing blocks as in [9]. Exchanging multipliers with adders is advantageous because adders weigh less than multipliers in terms of silicon area. Due to reduction of multipliers, will get low area and high speed fir filter.
The explosive growth of multimedia application, the demand for high-performance and low-power digital signal processing (DSP) is getting higher and higher. The FIR digital filter in [9] is one of the most widely used fundamental devices performed in DSP systems, ranging from wireless communications to video and image processing. Some applications need the FIR filter to operate at high frequencies such as video processing,whereas some other applications request high throughput with a low-power circuit such as multiple-input– multipleoutput systems used in cellular wireless communication. Furthermore in[14], when narrow transition band characteristics are required, the much higher order in the FIR filter is unavoidable. Due to its linear increase in the hardware implementation cost brought by the increase in the block size L, the parallel processing technique loses its advantage to be employed in [12]. In a truncated multiplier, several of the least significant columns of bits in the partial product matrix are not formed.
This reduces the area and power consumption of the multiplier. It also reduces the delay of the multiplier in many cases, because the modified carry save adder producing the product can be shorter for the Modified Wallace reduction method, once the partial product array (bits) is formed, adjacent rows are collected into nonoverlapping groups of three. Each group of three rows is reduced by Applying a full adder to each column that contains three bits, Applying a half adder to each column that contains two bits, and Passing any single bit columns to the next stage without processing. There are two basic fir structures, direct form and Transposed form as in [8].