# Performance of FIR Filter with Wallace Multiplier over FIR filter with Truncated Multiplier

Full Text Download |

**Abstract**

Performance analysis of finite impulse response
(FIR) designs are presented by the concept of modified
Wallace multipliers .This paper aims at reducing the
leakage current , delays and power consumption of Wallace
multiplier .This is accomplished by MCSA. An efficient
verilog HDL has been written, successfully simulated and
synthesized in Xilinx and the results shows that proposed
design achieves the best delay and power than existing
system which uses the concept of truncated multiplier.

**Keywords:**Faithful Rounding, Finite Impulse Response
(FIR) filters, Truncated Multipliers, VLSI.

**I.Introduction **

Finite impulse response (FIR) digital filters are one
of the most widely used fundamental devices performed in
DSP systems, ranging from wireless communications to
video and image processing. This paper proposes new
parallel FIR filter structures, which are beneficial to
symmetric coefficients in terms of the hardware cost, under
the condition that the number of taps is a multiple of 2 or
3. The 5 parallel FIR structures gives low area and high
speed compare to existing 4 parallel architecture , exploit
the inherent nature of symmetric coefficients reducing half
the number of multipliers in sub filter section at the
expense of additional adders in preprocessing and post
processing blocks as in [9]. Exchanging multipliers with
adders is advantageous because adders weigh less than
multipliers in terms of silicon area. Due to reduction of
multipliers, will get low area and high speed fir filter.

The explosive growth of multimedia application,
the demand for high-performance and low-power digital
signal processing (DSP) is getting higher and higher. The
FIR digital filter in [9] is one of the most widely used
fundamental devices performed in DSP systems, ranging
from wireless communications to video and image
processing. Some applications need the FIR filter to
operate at high frequencies such as video processing,whereas some other applications request high throughput
with a low-power circuit such as multiple-input– multipleoutput
systems used in cellular wireless communication.
Furthermore in[14], when narrow transition band
characteristics are required, the much higher order in the
FIR filter is unavoidable. Due to its linear increase in the
hardware implementation cost brought by the increase in
the block size L, the parallel processing technique loses its
advantage to be employed in [12]. In a truncated multiplier,
several of the least significant columns of bits in the partial
product matrix are not formed.

This reduces the area and power consumption of the
multiplier. It also reduces the delay of the multiplier in
many cases, because the modified carry save adder
producing the product can be shorter for the Modified
Wallace reduction method, once the partial product array
(bits) is formed, adjacent rows are collected into nonoverlapping
groups of three. Each group of three rows is
reduced by Applying a full adder to each column that
contains three bits, Applying a half adder to each column
that contains two bits, and Passing any single bit columns
to the next stage without processing. There are two basic
fir structures, direct form and Transposed form as in [8].

## References:

- J. G. Chung and K. K. Parhi, “Frequency-spectrumbased low-area low-power parallel FIR filter design,” EURASIP J. Appl. Signal Process. , vol. 2002, no. 9, pp. 444–453, 2002.
- K. K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation. New York: Wiley, 1999.
- Z.-J. Mou and P. Duhamel, “Short-length FIR filter and their use in fast nonrecursive filtering,” IEEE Trans. Signal Process. , vol. 39, no. 6, pp. 1322–1332, Jun. 1991.
- J. I. Acha, “Computational structures for fast implementation of L-path and L-block digital filter,” IEEE Trans. Circuit Syst. , vol. 36, no. 6, pp. 805–812, Jun. 1989.
- C. Cheng and K. K. Parhi, “Hardware efficient fast parallel FIR filter structures based on iterated short convolution,” IEEE Trans. Circuits Syst. I, Reg. Papers , vol. 51, no. 8, pp. 1492–1500, Aug. 2004.
- C. Cheng and K. K. Parhi, “Further complexity reduction of parallel FIR filter,” in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS 2005), Kobe, Japan, May 2005.
- O. Gustafsson, “Lower bounds for constant multiplication problems,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 54, no. 11, pp. 974–978, Nov. 2007.
- Y. Voronenko and M. Puschel, “Multiplier less multiple constant multiplication,” ACM Trans. Algorithms, vol. 3, no. 2, pp. 1–38, May 2007.
- D. Shi and Y. J. Yu, “Design of linear phase FIR filters with high probability of achieving minimum number of adders,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 58, no. 1, pp. 126–136, Jan. 2011.
- R. Huang, C.-H. H. Chang, M. Faust, N. Lotze, and Y. Manoli, “Sign extension avoidance and word-length optimization by positive-offset representation for FIR filter design,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 58, no. 12, pp. 916–920, Oct. 2011.
- P. K. Meher, “New approach to look-up-table design and memory-based realization of FIR digital filter,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 3, pp. 592– 603, Mar. 2010.
- P. K. Meher, S. Candrasekaran, and A. Amira, “FPGA realization of FIR filters by efficient and flexible systolization using distributed arithmetic,” IEEE Trans. Signal Process. vol. 56, no. 7, pp. 3009–3017, Jul. 2008.
- Deepshikha Bharti, K. Anusudha, “High Speed FIR Filter Based on Truncated Multiplier and Parallel Adder” International Journal of Engineering Trends and Technology (IJETT) – Volume 5 Number 5 - Nov 2013
- S. Karunakaran, Dr. N.Kasthuri, “Area and Power Efficient VLSI Architecture for FIR Filter using Asynchronous Multiplier,” British Journal of Science 61 December 2011, Vol. 2
- Muhammad H. Rais, member IEEE “Efficient Hardware Realization of Truncated Multipliers using FPGA” International Journal of Engineering and Applied Sciences 5:2 2009
- Shen-Fu Hsiao, Jun-Hong Zhang Jian, and Ming-Chih Chen “Low-Cost FIR Filter Designs Based on Faithfully Rounded Truncated Multiple Constant Multiplication/Accumulation” IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—ii: express briefs, vol. 60, no. 5, may 2013.