VHDL Simulation of DWT for Low Level Image Processing Application

Abstract
Discrete wavelet transform (DWT) is the one of the main approaches used for image compression. A new discrete wavelet transform (DWT) architecture is proposed in this paper to realize a memory-efficient 2D DWT unit. The main goal of the proposed system is to change the processing unit in the pipelined DWT. Processing unit is modified in such a way that total number of processing required in the system will be reduced. The hardware is efficiently reduced by using the concept of intra-stage parallelism and inter-stage parallelism. The intra-stage parallelism is obtained by dividing the 2D filtering operation into four tasks. The multi decomposition levels in the stage of pipeline are mapped by computational task in inter-stage parallelism. To maintain the critical path delay serially concatenated additions are optimized by changing computation topology and applying arithmetic optimization. The Proposed architecture computes DWT efficiently with less clock cycles. The hardware complexity of 2D DWT is significantly reduced.
Keywords:discrete wavelet transforms, Computational parallelism, inter-stage parallelism, intra-stage parallelism, multi resolution filtering.
I.Introduction
The multi-resolution decomposition approach is an effective approach to analyze the information present in the content of the image.2D discrete wavelet transform gives the multiresolution decomposition capability [1]. The 2D discrete wavelet transform involves computation of large volumes of data and processing them in various decomposition levels is overhead. Earlier, many studies have been done to improve the performance of 2-D DWT computation which effectively utilizes the hardware resources. The architectures proposed earlier can be broadly classified into separable [2]–[16] and non-separable architectures [17]–[27]. Earlier can be broadly classified into separable [2]–[16] and non-separable architectures [17]–[27].
A separable architecture is one where a 2-D filtering operation is divided into two 1-D filtering operations, one for processing the data row-wise and the other column-wise. A low-storage short-latency separable architecture where the row-wise operations are performed by systolic filters and the column-wise operations are performed in parallel filters has been proposed in [2]. This architecture requires complex control units to facilitate the interleaved operations of the output samples of different decomposition levels by employing a recursive pyramid algorithm (RPA) [3]. A scheme which leads to low complexity architecture with large latency have been proposed by Liao et al. [3] in which each of the row- and column-wise filtering operations are decomposed using the so called lifting operations [29] into a cascade of sub-filtering operations. As the 2D transforms are computed directly by using 2D filters in non-separable architectures, they do not have this problem. Two nonseparable architectures based on a modified RPA have been proposed by Chakrabarti et al. [17]. One using parallel 2-D filters where high degree of computational parallelism is achieved at the expense of less efficient hardware utilization. Second using SIMD 2-D architecture requires a reconfigured organization of the array as the processing moves on to higher decomposition levels. Cheng et al. [18] have proposed an architecture which improves the processing speed at the expense of increased hardware by using a number of parallel FIR filters with a polyphase structure. Hung et al. [19] have proposed an architecture that is a pipeline of one stage of parallel multipliers and two stages of accumulators to perform the accumulation tasks of the filters in each of the two directions. This architecture provides a reduced count of multipliers and to facilitate the processing of the boundary data. The processing speed of this architecture is low as same architecture is utilized recursively to perform the tasks of successive decomposition levels. Marino [21] has proposed a two-stage pipeline architecture which provides short computation time where first stage performs the task of the first decomposition level and the second one that of all the remaining levels. The complexity of the hardware resources is high and design is complicated as the processing units employed in this architecture differ from one another.