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High Performance of LMS Adaptive Filter Using LUT

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The presents an efficient implementation of adaptive filter by minimizing the area and the power consumed with the use of least mean square algorithm. The memory based structures are replaced with the MAC units in order to achieve the optimized area and power. The LUTs are memory based units used for the design of the filter.
Keywords:MAC, LUT, memory, adaptive filter.
The term ‘filter’ is often applied to any device or system that processes incoming signals or other data in such a way as to eliminate noise, or predict the next input signal from moment to moment[1] . During the last decades the adaptive filters have attracted many researches due to the property of their selfdesigning. Hence, an adaptive filter is a computational device that attempts to model the relationship between two signals in an iterative manner. Adaptive filters are often realized either with a set of logic operations implemented on a field programmable gate array (FPGA) or with a set of programming instructions running on a microprocessor or on a digital signal processor. The adaptive filter is defined by 4 main aspects: 1. The signal processed by a filter. 2. The structure defines how the output of the filter is computed from its input signal. 3. The parameters within this structure that can be iteratively changed to alter the filter’s input-output relationship. 4. The algorithm that describes how the parameters are adjusted from one time instant to next. The adaptive filtering consists of 2 basic operations: the filtering process and adaptation process. In filtering process, an output signal is generated from an input data signal using a digital filter. In the adaptation process, consists of an adaptation algorithm which adjusts the coefficients of the filter to minimize the desired function.
An efficient adaptive filter has being designed and simulated using Xilinx so comparing with the literature survey [2], the area and the power has been minimized.


  1. Introduction to adaptive filter by Douglas B.Williams, 1999.
  2. On Adaptive Least Mean Square FIR filter: New implementations and applications, Tampere, 2004.
  3. Adaptive Filters by Bernard Widrow, 1971.
  4. Adaptive filter architecture for FPGA architecture by Joseph G.Petrone, 2004.
  5. S. Haykin and B. Widrow, 2003, Least-Mean-Square Adaptive Filters. Hoboken, NJ, USA: Wiley.
  6. D. J. Allred, H. Yoo, V. Krishnan, W. Huang, and D. V. Anderson, Jul. 2005, “LMS adaptive filters using distributed arithmetic for high throughput,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 7, pp. 1327–1337.
  7. Y. Voronenko and M. Puschel, May 2007l, “Multiplier less multiple constant multiplication,” ACM Trans. Algorithms, vol. 3, no. 2, pp. 1–38.
  8. P. K. Meher, S. Candrasekaran, and A. Amira, Jul. 2008, “FPGA realization of FIR filters by efficient and flexible systolization using distributed arithmetic,” IEEE Trans. Signal Process., vol. 56, no. 7, pp. 3009– 3017.
  9. P. K. Meher, Jul. 2008, “New approach to look-up-table design and memory-based realization of FIR digital filter,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 3, pp. 592–603.
  10. P. K. Meher, April 2010, ‘LUT Optimization for Memory-Based Computation,’ IEEE Trans on Circuits & Systems-II, pp.285-289.
  11. P. K. Meher, September 2010, ‘Novel Input Coding Technique for High-Precision LUT Based Multiplication for DSP Applications’ The18th IEEE/IFIP International Conference on VLSI and System-onChip (VLSI-SoC 2010), pp. 201-206, Madrid, Spain.
  12. P. K. Meher, September 2010, ‘An Optimized Lookup-Table for the Evaluation of Sigmoid Function for Artificial Neural Networks’ The18th IEEE/IFIP International Conference on VLSI and System-onChip (VLSI-SoC 2010), pp. 91-95, Madrid, Spain,