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Low Power, High Throughput Adaptive FIR Filter Designed for Real Time Audio Denoising

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Adaptive filters find extensive use in many signal processing applications such as channel equalization, echo processing, noise cancellation etc. It can be implemented using one or more multiply and accumulate (MAC) units. But the Memory-based structures provides better performance in area minimization compared with multiply-accumulate structures and have many other advantages such as reduced latency since the memory-access-time is much shorter than the usual multiplication-time compared to the conventional multipliers. So the efficient memory computing system alternative to conventional logic computing is required in many DSP applications. The LUT designed using combined APC-OMS technique is used. This APC-OMS technique reduces the LUT size to one-fourth of its original area. If conventional LUT is used, the on-chip memory size is getting larger. The memory size can be reduced by decomposing the LUT. FIR filter is designed using multiplexer which is used to select the filter coefficients. Hence, the combination of these two techniques provides reduction in LUT size to one fourth in adaptive FIR filter when compared with the conventional Look up Table (LUT) of adaptive FIR filter. By the proposed method, area efficiency and throughput is achieved. The filter designs are simulated using Modelsim6.4a and are synthesized using Quartus II 9.0.
Index Terms: Distributed arithmetic, FIR filter, throughput, Memory-based implementation, UT-multiplier-based approach
Adaptive filters find extensive use in many signal processing applications such as channel equalization, echo processing, noise cancellation etc. Such filters typically involve finite impulse response (FIR) filters whose weights are updated according to some minimizing criteria[1]. FIR filters can be implemented using one or more multiply and accumulate (MAC) units since the output of the filter is the weighted sum of input samples but this would be time consuming and multiple MAC units may increase the system complexity. Several attempts have been made in order to implement adaptive filters using reduction techniques where the filter weights are updated once for each output block[2]. Later, pipelined architectures using look-ahead and relaxed look-ahead have been proposed in order to implement high sampling rate adaptive filters[3]-[4]. They proved to be effective but the pipelining or parallel implementations either produce adaptation delays or increase the hardware requirement. In order to overcome this, the first frequency domain adaptive filter has been proposed where a smaller block delay is maintained by using smaller block sizes. Once again the pipelining technique has been adopted but this time without the adaptation delay and degradation in the convergence performance. With semi-conductor memories becoming more cheaper and much faster since the memory access time is much less than the propagation delay, there is an inclination in the field of research towards the use of semiconductor memories. Distributed arithmetic is a preferable method since it can realize large filters without hardware multipliers to produce very high throughputs[5]. Few attempts have been made in order to implement adaptive filters based on the funcion of DA. The look-up-tables with special addressing produces the high throughput. Finite Impulse Response (FIR) filters are one of the key building blocks of many signal processing applications in communication systems. Channel equalization, interference cancellation and matched filtering are some variety of FIR filter applications. Hence, the programmable and reconfigurable FIR filter architectures are needed for next generation communication systems with low power consumption, low complexity and high speed operation requirements. The major bottleneck in FIR filter implementation is coefficients multipliers, which are traditionally implemented by add/sub/shift operations. Digital filters are the essential units for digital signal processing systems. Traditionally, digital filters are achieved in Digital Signal Processor(DSP), but DSP-based solution cannot meet the high speed requirements in some applications for its sequential structure. Nowadays, Field Programmable Gate Array (FPGA) technology is widely used in digital signal processing area because FPGA-based solution can achieve high speed due to its parallel structure and configurable logic, which provides great flexibility and high reliability in the course of design and later maintenance. Several architectures have been reported in the literature for memory-based implementation of DSP algorithms involving orthogonal transforms and digital filters [8]. However, we do not find any significant work on LUT optimization for memory-based multiplication and have presented a new approach to LUT design, where only the odd multiples of the fixed coefficient are required to be stored[9],,
We have suggested an efficient architecture for low-power, high-throughput, and low-area implementation of adaptive fir filter. Throughput rate is significantly enhanced by parallel LUT update and concurrent processing of filtering operation and weight-update operation. From the synthesis results, we find that the proposed design consumes less area and power over our previous DA-based FIR adaptive filter in average for different filter lengths. The design and implementation of a Digital audio broadcasting system (DABS) over a Field Programmable Gate Array (FPGA) platform for low bit rate voice communication using Audio codec has higher possibility of noises. Low bit rate voice communication has become essential to many applications like digital radio, satellite communication, underwater acoustic communication etc., where bandwidth is at a premium and voice intelligibility is imperative. For better audio quality, we are going to implement our proposed FIR with audio codec suitable for mobile communication and radio broadcasting.


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